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benchmarks: m1max studio added to fleet MLX matrix - 7.1 TF, 336 GB/s second-best bandwidth

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Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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m3ultra 2026-07-19 00:35:15 +10:00
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BENCHMARKS.md
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@ -168,3 +168,12 @@ Verdicts:
- **head_dim pad-to-64 matters MOST on newest chips** (M5 4.7×!, M4-class ~1.3-1.6×, M3 Ultra 1.5×) and ~zero on M1-class (no fused fast path there anyway — matches the corridorkey ablation).
- Fleet total ≈ 59 TFLOPS fp16; the two Ultras are 2/3 of it. TRELLIS.2-MLX lane assignment: m3ultra primary, ultra second (fp16), M4 Pro light ops.
- Probe script: reusable one-liner via `uv run --with mlx` — mlxprobe.py (this bench).
Addendum (same day) — m1max studio joins the matrix (login `studio@100.92.78.24`;
the fleet doc's `m1max@` user and "disk-critical" note are both stale — 170GB free):
| M1MAX | M1 Max | 32 | 7.09 | 6.04 | 336 | 1.22× |
Notable: 2nd-best bandwidth in the fleet (336 GB/s > M4 Pro's 225) despite mid-pack
compute — good fit for memory-bound MLX work (VAE decode, big-tensor elementwise).
Fleet total ≈ 66 TFLOPS fp16 across 7 machines.