db2097c19f
Final ordering at 128^3/128ch now tracks GPU core count, which is the evidence the op is genuinely compute-bound rather than dispatch-bound: m3ultra (80c) 13.8ms | m2max (38c) 27.3ms | m1ultra (64c) 39.7ms | m1max (32c) 41.4ms m4pro reachable by ICMP but not ssh (key/user), and it is HANDS OFF per fleet rules, so it is excluded rather than provisioned.
114 lines
5.1 KiB
Markdown
114 lines
5.1 KiB
Markdown
# lato.2_mrp_mlx
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An MLX port of [LATO.2](https://github.com/LoHhhha/LATO.2) — factorised 3D mesh generation
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(vertex flow, then connectivity flow) — so it runs natively on Apple Silicon.
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## Why
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LATO.2 generates meshes to a **controllable vertex budget**, which is the interesting part:
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it sidesteps the generate-dense-then-decimate loop that TRELLIS-style pipelines force on
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you. But upstream inherits TRELLIS.2's `setup.sh` and hard-requires CUDA:
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```python
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# upstream modules/sparse/__init__.py
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BACKEND = 'spconv' # accepts only ['spconv', 'torchsparse'] — both CUDA-only
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ATTN = 'flash_attn' # accepts only ['xformers', 'flash_attn'] — both CUDA-only
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```
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No SDPA fallback, no MPS path. Neither sparse backend has a Metal build.
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## The scope, once measured
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The CUDA surface is far smaller than `setup.sh --all` implies. Of the seven released
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checkpoints, five are entirely dense. Sparse code touches only `vertex_autoencoder` and
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`vertex_structured_flow`, and **every** `SparseConv3d` in the model is constructed with the
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defaults `stride=1, padding=None` — which upstream dispatches to `SubMConv3d`.
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So the whole blocker is one operation: **submanifold 3×3×3 convolution**.
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| Upstream | Here |
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| `spconv.SubMConv3d` | `lato_mlx/sparse/conv.py` — gather/scatter over a sorted-key indice map |
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| `SparseInverseConv3d` | never instantiated upstream; not needed |
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| strided sparse conv | never used; upsampling is `SparseSubdivide` (coord expansion ×8) |
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| `nn.Conv3d` (voxel encoder) | dense, maps to `mlx.nn.Conv3d` |
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| `flash_attn` / `xformers` | `attn_mode="full"` everywhere → plain SDPA |
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## Status
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- [x] `SparseTensor` container + `subdivide`
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- [x] `SubMConv3d` (k=3 and k=1) — **7/7 correctness tests pass**, max err 3e-7 vs an
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independent naive reference
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- [x] Weight converter, all 7 checkpoints → MLX safetensors (3.3 GB)
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- [ ] Remaining sparse ops: `SparseLinear`, `SparseGroupNorm32`, activations, attention
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- [ ] Model graphs: V-VAE, V-Flow, T-VAE, T-Flow, encoders
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- [ ] End-to-end inference
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- [ ] Fleet benchmark (m1max / m2max / m4pro / m1ultra / m3ultra)
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## Fleet benchmark
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`SubMConv3d` at 128³ grid, 128 channels, ~10% occupancy (209,715 voxels) — the hot op
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in the V-VAE. `conv_ms` is GPU work with a warm indice cache.
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| box | chip | GPU cores | conv_ms | Mvox/s |
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|---|---|---|---|---|
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| m3ultra | M3 Ultra | 80 | **13.8** | 15.25 |
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| m2max | M2 Max | 38 | 27.3 | 7.69 |
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| m1ultra | M1 Ultra | 64 | 39.7 | 5.28 |
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| m1max | M1 Max | 32 | 41.4 | 5.06 |
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Getting there took two rounds, both of which the fleet data — not local profiling —
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made visible:
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| version | m3ultra | note |
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| per-offset loop | 81.6 ms | *slower than a 38-core M2 Max* |
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| fused gather + matmul | 39.3 ms | 2.1× |
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| cached device index | **13.8 ms** | 5.9× total |
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The first version was launch-latency bound: 2·K³ = 54 tiny dispatches per layer, none
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large enough to occupy the GPU. The giveaway was throughput being *anti-correlated* with
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core count — the 80-core Ultra lost to every smaller box, because its fused-die design
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punishes small dispatches hardest. Fusing the taps into one `[N,K³·Cin]×[K³·Cin,Cout]`
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matmul fixed the dispatch count; caching the prepared device index removed ~26 ms of
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per-layer numpy bookkeeping that was hiding behind ~13 ms of real GPU work.
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Only after both did core count start predicting performance, which is the sign the op is
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finally compute-bound. Note the M1 Ultra (64 cores) still barely beats the M1 Max (32) —
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gather-heavy work scales poorly across UltraFusion.
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**Next target:** the indice map is now dominant (232–357 ms, CPU numpy) and is only
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amortised because it is cached per coordinate set. It matters whenever coordinates change.
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## Correctness
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`spconv` cannot be installed here — that is the reason this port exists — so there is no
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numerical diff against upstream. Instead `tests/test_sparse.py` checks the vectorised
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implementation against a deliberately naive one written straight from the definition
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(dict lookup, per-voxel loop). They share no indexing code, so an off-by-one cannot hide
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in both. Tests also cover batch isolation, isolated voxels, and indice-map hit rates.
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**One assumption remains unverified**: whether spconv gathers `feats[c+d]`
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(cross-correlation — the deep-learning convention, and what this implements) or
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`feats[c-d]`. A flipped kernel is numerically silent. It gets settled end-to-end: the
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V-VAE is an autoencoder, so a clean reconstruction confirms the orientation. Run the
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converter with `--flip-kernel` to test the alternative without touching code.
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## Use
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```bash
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uv venv --python 3.12 .venv
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VIRTUAL_ENV=.venv uv pip install mlx numpy torch trimesh
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hf download 0x4c48/LATO.2 --local-dir ckpt # 3.3 GB upstream weights
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.venv/bin/python -m lato_mlx.convert --ckpt ckpt --out weights
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.venv/bin/python tests/test_sparse.py
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```
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Upstream source is vendored read-only under `upstream/LATO.2` for reference.
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## Licence
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Upstream LATO.2 is MIT (Copyright the LATO.2 authors); its sparse module carries
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Microsoft and VAST-AI-Research copyright, also MIT. This port is MIT on the same terms.
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