trellis_sparse_mrp_mlx/bench/m1max.json
John 70cd436eb9 Shared TRELLIS-lineage sparse core in MLX
Extracted from lato.2_mrp_mlx. The same sparse module underlies LATO.2, Pixal3D and
the rest of the TRELLIS.2 family, and all of them are blocked on Apple Silicon by the
same single op - submanifold conv - so it belongs in one tested package rather than
vendored per port.

13/13 tests: 7 for the conv against a hand-written reference (spconv is uninstallable
here so there is no upstream oracle), 6 for the remaining layers against torch.

SubMConv3d runs 13.8ms at 128^3/128ch on m3ultra, 5.9x faster than the obvious
per-offset loop.
2026-08-02 10:31:07 +10:00

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{
"machine": {
"host": "M1MAX",
"chip": "Apple M1 Max",
"ram_gb": 34,
"mlx": "0.32.0"
},
"occupancy": 0.1,
"rows": [
{
"res": 32,
"channels": 64,
"voxels": 3276,
"imap_ms": 4.740834003314376,
"conv_ms": 0.7942919619381428,
"mvox_s": 4.12442798993744
},
{
"res": 64,
"channels": 64,
"voxels": 26214,
"imap_ms": 36.672832909971476,
"conv_ms": 2.2925420198589563,
"mvox_s": 11.434468713298768
},
{
"res": 64,
"channels": 128,
"voxels": 26214,
"imap_ms": 35.68366612307727,
"conv_ms": 5.524750100448728,
"mvox_s": 4.744829996540633
},
{
"res": 128,
"channels": 128,
"voxels": 209715,
"imap_ms": 319.13441605865955,
"conv_ms": 41.41504201106727,
"mvox_s": 5.063739883300329
}
]
}