15a5e74434
Pixal3D refactored the container into a VarLenTensor base (feats + explicit slice-per-batch layout, no coords) with SparseTensor(VarLenTensor) adding coordinates. LATO.2 has only the combined class. Modelling the split here means one package serves both without either port adapting at every call site. Also exposes Pixal3D's cache spelling (get/register_spatial_cache) alongside LATO.2's (cache_get/cache_put). 13/13 tests unchanged.
39 lines
1.4 KiB
Python
39 lines
1.4 KiB
Python
"""MLX implementation of the TRELLIS-lineage sparse module.
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Microsoft's TRELLIS.2 sparse stack has been inherited, near-verbatim, by a growing
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family of 3D generation models — LATO.2 and TencentARC's Pixal3D among them. All of
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them hard-require spconv or torchsparse, neither of which has a Metal build, and that
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single dependency is what keeps the whole lineage off Apple Silicon.
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The blocker is one operation: submanifold 3x3x3 convolution. Every SparseConv3d in
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these models is constructed `stride=1, padding=None`, which spconv dispatches to
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SubMConv3d. Implement that in MLX and the rest is ordinary linear/norm/attention work.
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Packaged separately from any one model so each port depends on a tested core rather
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than vendoring its own copy.
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"""
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from .conv import SubMConv3d, build_indice_map
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from .tensor import SparseTensor, VarLenTensor, downsample, subdivide
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from .ops import (
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LayerNorm32,
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SparseFeedForwardNet,
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SparseGELU,
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SparseGroupNorm32,
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SparseLinear,
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SparseMultiHeadAttention,
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SparseResBlock,
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SparseSiLU,
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SparseTransformerBlock,
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SparseTransformerCrossBlock,
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)
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__all__ = [
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"SparseTensor", "VarLenTensor", "subdivide", "downsample",
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"SubMConv3d", "build_indice_map",
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"SparseLinear", "LayerNorm32", "SparseGroupNorm32", "SparseSiLU", "SparseGELU",
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"SparseResBlock", "SparseFeedForwardNet", "SparseMultiHeadAttention",
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"SparseTransformerBlock", "SparseTransformerCrossBlock",
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]
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__version__ = "0.1.0"
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