trellis_sparse_mrp_mlx/bench/m3ultra_fused.json
John 70cd436eb9 Shared TRELLIS-lineage sparse core in MLX
Extracted from lato.2_mrp_mlx. The same sparse module underlies LATO.2, Pixal3D and
the rest of the TRELLIS.2 family, and all of them are blocked on Apple Silicon by the
same single op - submanifold conv - so it belongs in one tested package rather than
vendored per port.

13/13 tests: 7 for the conv against a hand-written reference (spconv is uninstallable
here so there is no upstream oracle), 6 for the remaining layers against torch.

SubMConv3d runs 13.8ms at 128^3/128ch on m3ultra, 5.9x faster than the obvious
per-offset loop.
2026-08-02 10:31:07 +10:00

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{
"machine": {
"host": "m3ultra",
"chip": "Apple M3 Ultra",
"ram_gb": 275,
"mlx": "0.32.0"
},
"occupancy": 0.1,
"rows": [
{
"res": 32,
"channels": 64,
"voxels": 3276,
"imap_ms": 3.81183298304677,
"conv_ms": 1.5459590358659625,
"mvox_s": 2.1190729663577157
},
{
"res": 64,
"channels": 64,
"voxels": 26214,
"imap_ms": 28.528874972835183,
"conv_ms": 2.9240419971756637,
"mvox_s": 8.964987515678686
},
{
"res": 64,
"channels": 128,
"voxels": 26214,
"imap_ms": 28.55800004908815,
"conv_ms": 6.438167009036988,
"mvox_s": 4.071655793210163
},
{
"res": 128,
"channels": 128,
"voxels": 209715,
"imap_ms": 237.24404198583215,
"conv_ms": 39.25516700837761,
"mvox_s": 5.342354038520428
}
]
}