trellis_sparse_mrp_mlx/bench/m2max.json
John 70cd436eb9 Shared TRELLIS-lineage sparse core in MLX
Extracted from lato.2_mrp_mlx. The same sparse module underlies LATO.2, Pixal3D and
the rest of the TRELLIS.2 family, and all of them are blocked on Apple Silicon by the
same single op - submanifold conv - so it belongs in one tested package rather than
vendored per port.

13/13 tests: 7 for the conv against a hand-written reference (spconv is uninstallable
here so there is no upstream oracle), 6 for the remaining layers against torch.

SubMConv3d runs 13.8ms at 128^3/128ch on m3ultra, 5.9x faster than the obvious
per-offset loop.
2026-08-02 10:31:07 +10:00

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{
"machine": {
"host": "m2max",
"chip": "Apple M2 Max",
"ram_gb": 103,
"mlx": "0.32.0"
},
"occupancy": 0.1,
"rows": [
{
"res": 32,
"channels": 64,
"voxels": 3276,
"imap_ms": 5.0670419877860695,
"conv_ms": 0.9743330010678619,
"mvox_s": 3.362300154474423
},
{
"res": 64,
"channels": 64,
"voxels": 26214,
"imap_ms": 42.181833006907254,
"conv_ms": 2.3582500289194286,
"mvox_s": 11.115869682406615
},
{
"res": 64,
"channels": 128,
"voxels": 26214,
"imap_ms": 41.914000001270324,
"conv_ms": 3.8609580078627914,
"mvox_s": 6.789506631933196
},
{
"res": 128,
"channels": 128,
"voxels": 209715,
"imap_ms": 356.8419170042034,
"conv_ms": 27.282333001494408,
"mvox_s": 7.6868426167407575
}
]
}