trellis_sparse_mrp_mlx/bench/m1ultra.json
John 70cd436eb9 Shared TRELLIS-lineage sparse core in MLX
Extracted from lato.2_mrp_mlx. The same sparse module underlies LATO.2, Pixal3D and
the rest of the TRELLIS.2 family, and all of them are blocked on Apple Silicon by the
same single op - submanifold conv - so it belongs in one tested package rather than
vendored per port.

13/13 tests: 7 for the conv against a hand-written reference (spconv is uninstallable
here so there is no upstream oracle), 6 for the remaining layers against torch.

SubMConv3d runs 13.8ms at 128^3/128ch on m3ultra, 5.9x faster than the obvious
per-offset loop.
2026-08-02 10:31:07 +10:00

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{
"machine": {
"host": "ultra",
"chip": "Apple M1 Ultra",
"ram_gb": 137,
"mlx": "0.32.0"
},
"occupancy": 0.1,
"rows": [
{
"res": 32,
"channels": 64,
"voxels": 3276,
"imap_ms": 5.284500017296523,
"conv_ms": 2.137709001544863,
"mvox_s": 1.532481735181227
},
{
"res": 64,
"channels": 64,
"voxels": 26214,
"imap_ms": 39.58837501704693,
"conv_ms": 3.456457983702421,
"mvox_s": 7.584064416116698
},
{
"res": 64,
"channels": 128,
"voxels": 26214,
"imap_ms": 38.462458993308246,
"conv_ms": 4.72516700392589,
"mvox_s": 5.547740424459111
},
{
"res": 128,
"channels": 128,
"voxels": 209715,
"imap_ms": 349.49354198761284,
"conv_ms": 39.74312503123656,
"mvox_s": 5.276761699920983
}
]
}