trellis-2-mrp-mlx/trellis2/modules
Pedro Augusto 369cb6c6fe sparse/norm: CPU-staged zeros_like workaround for MPS
SparseGroupNorm / SparseLayerNorm used torch.zeros_like which fails with
"DispatchStub: missing kernel for mps" on PyTorch builds compiled with
both CUDA and MPS backends (the user's local build hit this). Added a
_zeros_like_safe helper that builds zeros on CPU and transfers when the
reference tensor is on MPS; Apple Silicon unified memory makes the
transfer metadata-only, so the overhead vs a working MPS zeros kernel
is negligible. On CPU, behaves identically to torch.zeros_like.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-07-17 07:51:05 +03:00
..
attention Init Release 2025-12-16 19:00:42 +00:00
sparse sparse/norm: CPU-staged zeros_like workaround for MPS 2026-07-17 07:51:05 +03:00
transformer Init Release 2025-12-16 19:00:42 +00:00
image_feature_extractor.py add mlx backend for apple silicon with metal gpu acceleration 2026-07-17 07:51:05 +03:00
norm.py Init Release 2025-12-16 19:00:42 +00:00
spatial.py Init Release 2025-12-16 19:00:42 +00:00
utils.py Init Release 2025-12-16 19:00:42 +00:00