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rung 3 results: 3.0x e2e (216.6->72.0s), 2.8x memory, parity held — sampler+baker+validator on the fork

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Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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m3ultra 2026-07-20 03:55:54 +10:00
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34
BENCHMARKS.md
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@ -398,3 +398,37 @@ family has mx.compile on denoise + compiled scheduler (the 9s/image path).
GAP: FLUX.1 family (dev/schnell/krea) has ZERO mx.compile — backport =
same env-gated pattern as Hunyuan T1/T2, modest expected win (1-4% M3U,
more on small boxes), upstreamable to mflux. Queued, not urgent.
## 12 · RUNG-3 KERNEL DAY — RESULTS (2026-07-20)
**Headline: 216.6s → 71.96s e2e (3.0×), peak 75.4GB → 26.5GB (2.8×),
parity held (raw mesh Δ0.03%), full gate EXIT=0.** All on the fork
(monster/trellis-2-mrp-mlx): fa972aa + 7860148 + 0db816b.
What actually moved the needle (in order of impact):
1. **Vertex baker properly wired into generate_asset** (scheduler
fallthrough fixed — `--baker vertex` was silently running the 5h
pure-python kdtree path): "other" bucket 69.4s → 8.3s, and the
75GB peak turned out to be the METAL BAKE's, not the conv's.
2. **Pure-MLX sampler loop** (mlx_samplers.py): torch CPU loop + per-
forward host bounces → one conversion per stage, batched dense CFG,
once-per-stage concat_cond. Sampling 56.8→54.4s (~4% — forwards are
compute-bound) but it is the correctness-proven, compile-ready
architecture, and removes ~72 host round-trips/gen.
3. **Validator taught the vertex-colored asset class** (COLOR_0 without
UVs = legit; normals materialized at export).
Honest negatives (documented so nobody re-chases them):
- mx.compile on the step forward: ~0 on M3 Ultra (GEMM-bound; matches
Hunyuan T1/T2 findings).
- Fused Metal sparse-conv kernel: built, parity 8e-4, but stock chunking
already bounds memory at decoder scale and beats the scalar kernel on
speed. Kept as TRELLIS2_METAL_SPCONV=1 opt-in reference (simdgroup
tiling = the future version if decoders ever matter for time).
- Remaining gap to H100 (~17s at 1024): inside the DiT forwards
(54s sampling ≈ 2.3× ideal FLOPs) — attention/MLP internals, a
future deep-dive, not orchestration.
Env knobs (all default-sane): TRELLIS2_MLX_SAMPLER=0 (revert sampler),
TRELLIS2_MLX_COMPILE=1, TRELLIS2_METAL_SPCONV=1.
M1 Ultra validation: in flight (26.5GB peak fits with 100GB headroom).

34
docs/FABLE_STARTUP_PACKET.md
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@ -466,3 +466,37 @@ quality gap closed for albedo. Not yet carried: metallic/roughness maps
(vertex colors are albedo-only) — MR needs the UV path (Option B) or a
COLOR_1 convention. MESHGOD finish-farm verts→texture bake = the
remaining Option-A step for game-budget assets.
## 12 · RUNG-3 KERNEL DAY — RESULTS (2026-07-20)
**Headline: 216.6s → 71.96s e2e (3.0×), peak 75.4GB → 26.5GB (2.8×),
parity held (raw mesh Δ0.03%), full gate EXIT=0.** All on the fork
(monster/trellis-2-mrp-mlx): fa972aa + 7860148 + 0db816b.
What actually moved the needle (in order of impact):
1. **Vertex baker properly wired into generate_asset** (scheduler
fallthrough fixed — `--baker vertex` was silently running the 5h
pure-python kdtree path): "other" bucket 69.4s → 8.3s, and the
75GB peak turned out to be the METAL BAKE's, not the conv's.
2. **Pure-MLX sampler loop** (mlx_samplers.py): torch CPU loop + per-
forward host bounces → one conversion per stage, batched dense CFG,
once-per-stage concat_cond. Sampling 56.8→54.4s (~4% — forwards are
compute-bound) but it is the correctness-proven, compile-ready
architecture, and removes ~72 host round-trips/gen.
3. **Validator taught the vertex-colored asset class** (COLOR_0 without
UVs = legit; normals materialized at export).
Honest negatives (documented so nobody re-chases them):
- mx.compile on the step forward: ~0 on M3 Ultra (GEMM-bound; matches
Hunyuan T1/T2 findings).
- Fused Metal sparse-conv kernel: built, parity 8e-4, but stock chunking
already bounds memory at decoder scale and beats the scalar kernel on
speed. Kept as TRELLIS2_METAL_SPCONV=1 opt-in reference (simdgroup
tiling = the future version if decoders ever matter for time).
- Remaining gap to H100 (~17s at 1024): inside the DiT forwards
(54s sampling ≈ 2.3× ideal FLOPs) — attention/MLP internals, a
future deep-dive, not orchestration.
Env knobs (all default-sane): TRELLIS2_MLX_SAMPLER=0 (revert sampler),
TRELLIS2_MLX_COMPILE=1, TRELLIS2_METAL_SPCONV=1.
M1 Ultra validation: in flight (26.5GB peak fits with 100GB headroom).