diff --git a/docs/MRP_MLX.md b/docs/MRP_MLX.md
index 260d8d2..6800f92 100644
--- a/docs/MRP_MLX.md
+++ b/docs/MRP_MLX.md
@@ -39,7 +39,7 @@ after the rung-3 kernel push; every number here was measured, not estimated.
 | m3ultra | M3 Ultra | 256GB | 23.5 | 400 GB/s | primary: TRELLIS.2, queue, heavy gen |
 | m1ultra | M1 Ultra | 128GB | 16.3 | 297 GB/s | second lane: everything (post rung-3) |
 | m1max | M1 Max | 32GB | 7.1 | 336 GB/s | bandwidth-friendly light ops |
-| m4pro | M4 Pro | 24GB | 5.2 | 225 GB/s | MB light ops + Ollama (hands off) |
+| m4pro | M4 Pro | 24GB | 5.2 | 225 GB/s | MB light ops + Ollama (24GB caps it) |
 
 Full 7-machine MLX matrix + probe script: `BENCHMARKS.md` (2026-07-19) +
 `scripts/mlxprobe.py`. Rules from it: **fp16 on M1-class** (bf16 −20%),