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type-two 35403f8f05 Lane B: tick Lane B done, session-5 completion summary + Lane C handoff 
PROGRESS.md: Lane B checked off with the session-5 outcome; SESSION 5 DONE block
(all 6 orders) + explicit Lane C handoff (BVH axes, skel_to_mixamorig map, camera
root_space, --from-params). B_ENGINE_SETUP.md: pose_engine.py usage + the engine
facts learned (SKEL 46-q, rest-aware FK ~4cm, Y-down camera fix, mobilenet detector).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-17 10:42:28 +10:00
docs Lane B: tick Lane B done, session-5 completion summary + Lane C handoff 2026-07-17 10:42:28 +10:00
engine_patches Lane B / session-5 item 5: pose_engine.py — SKEL BVH + sidecar (B2) + jitter (B3) 2026-07-17 10:41:08 +10:00
spec Lane B / session-5 item 5: pose_engine.py — SKEL BVH + sidecar (B2) + jitter (B3) 2026-07-17 10:41:08 +10:00
.gitignore Lane B: resolve decision gate -> Path B (local HSMR/SKEL, accept NC risk) 2026-07-17 02:25:55 +10:00
CLAUDE.md Lane 0: bootstrap MOCAPGOD 2026-07-17 00:40:26 +10:00
ingest.py Lane B / session-5 item 3: default ingest to local queue/ on ultra 2026-07-17 10:02:16 +10:00
PLAN.md Lane B / session-5 item 4: treaty amendment — required root_space sidecar field 2026-07-17 10:02:53 +10:00
pose_engine.py Lane B / session-5 item 5: pose_engine.py — SKEL BVH + sidecar (B2) + jitter (B3) 2026-07-17 10:41:08 +10:00
PROGRESS.md Lane B: tick Lane B done, session-5 completion summary + Lane C handoff 2026-07-17 10:42:28 +10:00
setup_hsmr.sh Lane B / session-5 item 1: durable-ize the ARM engine fixes into git 2026-07-17 09:34:39 +10:00