corridorkey-mrp-mlx/docs/plans
cmoyates e91089a804
docs: wave2 ablation benchmarks + optimization plan + brainstorm
Ablation sweep across 512/1024/2048 resolutions with 8 configs.
Tiled 768/64 = 1.5x faster + 11.4x less memory vs full-frame at 2048.
stage_gc net negative at small res, breaks even at 2048.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-03-09 19:32:04 -02:30
..
2026-03-01-feat-2048-smoke-test-plan.md feat: add 2048 smoke test for native-resolution validation 2026-03-01 07:04:28 -03:30
2026-03-01-feat-corridorkey-mlx-inference-port-plan.md feat(phase6): optimization, benchmarking, and tiled inference 2026-03-01 06:24:10 -03:30
2026-03-01-feat-engine-integration-surface-plan.md feat: add CorridorKeyMLXEngine integration surface 2026-03-01 06:43:07 -03:30
2026-03-01-fix-converter-review-feedback-plan.md feat(phase3): PyTorch→MLX weight converter (#1) 2026-03-01 05:16:56 -03:30
2026-03-01-phase4-hiera-backbone-plan.md feat(phase4): MLX Hiera backbone port (#2) 2026-03-01 05:55:24 -03:30
2026-03-03-refactor-deep-modules-plan.md docs: add deep modules refactor plan 2026-03-03 09:45:43 -03:30
2026-03-08-feat-mlx-memory-optimizations-plan.md chore: default bf16+fused decode on, add benchmark results to plan 2026-03-08 21:27:56 -02:30
2026-03-09-feat-mlx-optimization-wave2-plan.md docs: wave2 ablation benchmarks + optimization plan + brainstorm 2026-03-09 19:32:04 -02:30