corridorkey-mrp-mlx/docs/plans
cmoyates 57c3aff913
feat(phase6): optimization, benchmarking, and tiled inference
- Cache nn.Upsample instances in DecoderHead/GreenFormer __init__
  (eliminated ~7 allocations per forward pass)
- Add mx.compile() support via load_model(compile=True)
- Benchmark harness: eager vs compiled, multi-resolution, parity checks
- Tiled inference with overlap blending for large images
- Profiling utilities with forced mx.eval for accurate timing
- Reference comparison script (scripts/compare_reference.py)
- 12 new tests (compiled consistency + tiling)
- README performance section with Apple Silicon guidance

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-03-01 06:24:10 -03:30
..
2026-03-01-feat-corridorkey-mlx-inference-port-plan.md feat(phase6): optimization, benchmarking, and tiled inference 2026-03-01 06:24:10 -03:30
2026-03-01-fix-converter-review-feedback-plan.md feat(phase3): PyTorch→MLX weight converter (#1) 2026-03-01 05:16:56 -03:30
2026-03-01-phase4-hiera-backbone-plan.md feat(phase4): MLX Hiera backbone port (#2) 2026-03-01 05:55:24 -03:30